收藏本站
DS28DG02: 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog
is 1 AND the number if bits sent by the master is a multiple of 8 (i.e., full byte only), the write cycle (transfer from
the buffer to EEPROM) begins with the positive edge of CSZ. The duration of the write cycle is t PROG , during which
the RDYZ bit of the SPI Status register reads 1. After the write cycle is completed, the WEN bit is cleared. If the
target memory is write-protected OR WEN was not set to 1 before issuing the WRITE instruction OR the number of
data bits that followed the address byte was not a multiple of 8, the positive edge on CSZ does not start a write
cycle and the WEN bit is not cleared.
The six EEPROM registers, together with the reserved addresses, form another memory segment. Write access to
this segment is essentially the same as for the user memory with the following differences: The data sent by the
master that normally would apply to the first 10 bytes of the segment is discarded. A write cycle is initiated only if
the WEN bit of the SPI Status register is 1 AND the number if bits sent by the master is a multiple of 8 (i.e., full byte
only) AND at least one EEPROM byte is to be updated. If WEN was not set to 1 before issuing the WRITE
instruction OR the number of data bits that followed the address byte was not a multiple of 8 OR all data bytes sent
by the master applied to the nonwriteable addresses, the positive edge on CSZ does not start a write cycle and the
WEN bit is not cleared.
Write access to the SRAM, PIO, and NV SRAM does not involve a write buffer. If the WEN bit is 1 AND RPROT =
0 AND the target address is writeable, a data byte that follows the target address becomes effective as soon as its
transmission is completed. The address pointer increments after each data byte, directing subsequent bytes to the
next higher addresses. If the target address is read-only, data for that address is discarded. After address 135h is
updated, the address pointer wraps around to 120h. The master may continue sending data bytes indefinitely. The
write access ends with the positive edge on CSZ. The last byte, if incomplete, is ignored. The WEN bit is cleared
only if at least one byte was written to a writeable address. If RPROT = 1 the memory is not updated and the WEN
bit remains set. The RTC should be updated starting with the Seconds register. If the starting target address
specified after the instruction code points to the PIO Output State registers (address 120h or 121h) and the PIO
output mode OTM is 0 (low current) the address pointer toggles between 120h and 121h after the data byte is
transmitted. This allows fast PIO updates, e.g., for generating data patterns. For OTM = 1 (high-current) the
address pointer increments to the next higher address. For a PIO-update timing diagram and the differences
between low-current and high-current mode, see the PIO Read/Write Access section.
Upon receiving a write instruction with an address targeting the read-only memory or non-existing memory, all data
is discarded and no write cycle or data update takes place. Since the write access is not successful, the WEN bit in
the SPI Status register is not cleared.
As a precondition for a successful WRITE instruction, the WEN bit in the SPI Status register must be 1. The WEN
bit is set through the WREN instruction, which must be completed before the WRITE instruction. The WRITE timing
diagram for both SPI communication modes is shown in Figure 18 (single-byte write) and Figure 19 (multiple-byte
write). The programming time t PROG applies only to EEPROM writes. For writes to the SRAM, PIO, and NV SRAM in
SPI mode (0,0) the actual transfer to the target memory takes place on the falling SCK edge of the LS-bit of a data
byte. In SPI mode (1,1) the actual transfer to the target memory also takes place on the falling SCK edge of the LS-
bit of a data byte, except for the last byte, which is transferred on the rising edge of CSZ.
25 of 34
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*
相关PDF资料
DS28E04S-100+T IC EEPROM 4KBIT 16SOIC
DS28EC20+T IC EEPROM 20KBIT TO92-3
DS301X KWIK-CHG DESIGNATION STRIP SGL
DS3030W-100# IC NVSRAM 256KBIT 100NS 256BGA
DS3045W-100# IC NVSRAM 1MBIT 100NS 256BGA
DS3050W-100# IC NVSRAM 4MBIT 100NS 256BGA
DS3065W-100# IC NVSRAM 8MBIT 100NS 256BGA
DS3065WP-100IND+ IC SRAM 3.3V 8MB 34POWERCAP MOD
相关代理商/技术参数
DS28DG02EVKIT 功能描述:存储器 IC 开发工具 RoHS:否 制造商:STMicroelectronics 产品:Reference Boards 工具用于评估:M24LR64-R 存储容量:64 kbit 存储类型:EEPROM 工作电源电压:1.8 V to 5.5 V
DS28DG02G-3C+ 功能描述:电可擦除可编程只读存储器 2Kb SPI 电可擦除可编程只读存储器 w/PIO RTC/Rst/Bat Mtr/Wtdg RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8
DS28DG02G-3C+T 功能描述:电可擦除可编程只读存储器 2Kb SPI 电可擦除可编程只读存储器 w/PIO RTC/Rst/Bat Mtr/Wtdg RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8
DS28E01-100 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:带SHA-1引擎保护的1K位1-Wire EEPROM
DS28E01-100_12 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:1Kb Protected 1-Wire EEPROM with SHA-1 Engine
DS28E01-100+ 功能描述:电可擦除可编程只读存储器 RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8
DS28E01G-100+R 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:1K-Bit Protected 1-Wire EEPROM with SHA-1 Engine
DS28E01G-100+T 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:1K-Bit Protected 1-Wire EEPROM with SHA-1 Engine